A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien Hung Kuo; Cheng En Hsieh

doi:10.1109/ESSCIRC.2011.6045010

A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien Hung Kuo^*
, Cheng En Hsieh

^*此作品的通信作者

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

17 引文斯高帕斯（Scopus）

摘要

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

原文	英語
主出版物標題	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
頁面	475-478
頁數	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6045010
出版狀態	已發佈 - 2011
事件	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, 芬兰持續時間: 2011 9月 12 → 2011 9月 16

出版系列

名字	European Solid-State Circuits Conference
ISSN（列印）	1930-8833

其他

其他	37th European Solid-State Circuits Conference, ESSCIRC 2011
國家/地區	芬兰
城市	Helsinki
期間	2011/09/12 → 2011/09/16

UN SDG

此研究成果有助於以下永續發展目標

SDG 7 可負擔的潔淨能源

ASJC Scopus subject areas

硬體和架構
電氣與電子工程

存取文件

10.1109/ESSCIRC.2011.6045010

其它文件與鏈接

引用此

Kuo, CH & Hsieh, CE 2011, A high energy-efficiency SAR ADC based on partial floating capacitor switching technique. 於 ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6045010, European Solid-State Circuits Conference, 頁 475-478, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, 芬兰, 2011/09/12. https://doi.org/10.1109/ESSCIRC.2011.6045010

@inproceedings{f32d16a9a6ce4fac8c07a0931d7d1231,

title = "A high energy-efficiency SAR ADC based on partial floating capacitor switching technique",

abstract = "This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11\% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.",

author = "Kuo, \{Chien Hung\} and Hsieh, \{Cheng En\}",

year = "2011",

doi = "10.1109/ESSCIRC.2011.6045010",

language = "English",

isbn = "9781457707018",

series = "European Solid-State Circuits Conference",

pages = "475--478",

booktitle = "ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference",

note = "37th European Solid-State Circuits Conference, ESSCIRC 2011 ; Conference date: 12-09-2011 Through 16-09-2011",

}

TY - GEN

T1 - A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

AU - Kuo, Chien Hung

AU - Hsieh, Cheng En

PY - 2011

Y1 - 2011

N2 - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

AB - This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

UR - https://www.scopus.com/pages/publications/82955194670

UR - https://www.scopus.com/pages/publications/82955194670#tab=citedBy

U2 - 10.1109/ESSCIRC.2011.6045010

DO - 10.1109/ESSCIRC.2011.6045010

M3 - Conference contribution

AN - SCOPUS:82955194670

SN - 9781457707018

T3 - European Solid-State Circuits Conference

SP - 475

EP - 478

BT - ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference

T2 - 37th European Solid-State Circuits Conference, ESSCIRC 2011

Y2 - 12 September 2011 through 16 September 2011

ER -

A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

摘要

出版系列

其他

UN SDG

ASJC Scopus subject areas

存取文件

其它文件與鏈接

指紋

引用此