A high energy-efficiency SAR ADC based on partial floating capacitor switching technique

Chien-Hung Kuo*, Cheng En Hsieh

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

17 引文 斯高帕斯(Scopus)

摘要

This paper presents a new successive approximation register (SAR) analog-to-digital converter (ADC) with partial floating capacitor switching (PFCS) scheme for low-power data converters. By interchanging the switching order of the largest capacitor with the second largest one the switching energy consumption can be efficiently reduced. From the mathematical calculation result, the proposed technique achieves 96.11% less switching energy compared to the conventional approach. The presented 10-bit PFCS-based SAR ADC is implemented in a CMOS 0.18-μm 1P6M technology. The power consumption of the presented prototype is only 7.16-μW with a sampling rate of 1-MS/s at a supply voltage of 0.9-V and a 21.56-fF/conversion-step figure of merit is achieved.

原文英語
主出版物標題ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
頁面475-478
頁數4
DOIs
出版狀態已發佈 - 2011 十二月 12
事件37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, 芬兰
持續時間: 2011 九月 122011 九月 16

出版系列

名字European Solid-State Circuits Conference
ISSN(列印)1930-8833

其他

其他37th European Solid-State Circuits Conference, ESSCIRC 2011
國家/地區芬兰
城市Helsinki
期間2011/09/122011/09/16

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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