A frequency synthesizer using two different delay feedbacks

Chien Hung Kuo, Yi Shun Shih

研究成果: 雜誌貢獻Conference article

4 引文 斯高帕斯(Scopus)

摘要

A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time and nonidealities on PFD/CP. This PLL utilizes a tunable delay cell to reduce the ripple on the VCO control line and hence the jitter penalty. In addition, a fully differential delay cell for voltage-controlled oscillator (VCO) is introduced to perform a wide locking range and low-jitter performance. The proposed PLL was implemented in 0.35-μm 2P4M CMOS standard technology with the core area of 0.1 mm2. It can be operated from 250MHz to 1.29GHz and consume 38.2mW of power at 1GHz under a 3.3-V supply voltage.

原文英語
文章編號1465208
頁(從 - 到)2799-2802
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態已發佈 - 2005 十二月 1
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, 日本
持續時間: 2005 五月 232005 五月 26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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