A fast-locking DLL-based frequency multiplier for wide-range operation

Chien-Hung Kuo, Ching Shan Chien, Meng Feng Lin, Yen Cheng Tsai

研究成果: 書貢獻/報告類型會議貢獻

摘要

In this paper, a fast-locking delay-locked loop (DLL)-based frequency multiplier for wide-range operation is proposed. A programmable charging circuit (PCC) to the loop filter is developed to accelerate the locking time of DLL. In the presented DLL, the pseudo-differential delay cell is adopted in the voltage-controlled delay line (VCDL) for the suppression of the common-mode noise. Five clock cycles of the least lock time can be reached in the presented DLL. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2.1 GHz. The simulated cycle-to-cycle jitter of the DLL is 31 ps at 320 MHz of the reference input. The prototype circuit has been fabricated in a 0.18 μm 1P6M CMOS technology. The core area excluding PADs is 0.36×0.37 mm2. The power consumption of the proposed DLL is 24 mW from a 1.8 V of supply voltage.

原文英語
主出版物標題Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007
頁面105-110
頁數6
出版狀態已發佈 - 2007 十二月 1
事件5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007 - Banff, AB, 加拿大
持續時間: 2007 七月 22007 七月 4

出版系列

名字Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007

其他

其他5th IASTED International Conference on Circuits, Signals, and Systems, CSS 2007
國家加拿大
城市Banff, AB
期間07/7/207/7/4

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • 引用此

    Kuo, C-H., Chien, C. S., Lin, M. F., & Tsai, Y. C. (2007). A fast-locking DLL-based frequency multiplier for wide-range operation. 於 Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007 (頁 105-110). (Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007).