摘要
A double-sampling pseudo-two-path bandpass ΔΣ modulator is proposed. This modulator has an output rate equal to twice the dock rate, uses n/2 operational amplifier s (op-amps) for an nth-order noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass ΔΣ modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively.
| 原文 | 英語 |
|---|---|
| 頁(從 - 到) | 276-280 |
| 頁數 | 5 |
| 期刊 | IEEE Journal of Solid-State Circuits |
| 卷 | 35 |
| 發行號 | 2 |
| DOIs | |
| 出版狀態 | 已發佈 - 2000 2月 |
| 對外發佈 | 是 |
ASJC Scopus subject areas
- 電氣與電子工程
指紋
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