A D-Band Wideband Low-Noise Amplifier in 40-nm Bulk CMOS Technology with Doubly-Tuned Transformer Networks

This work presents a wideband D-band low-noise amplifier (LNA) realized in a 40-nm bulk CMOS technology. A five-stage differential common-source architecture is employed to achieve high gain and low noise figure (NF). Broadband interstage matching is accomplished using doubly-tuned transformer networks. The proposed LNA delivers a peak gain of 22.3 dB at 139.5 GHz and achieves a minimum NF of 6.2 dB at 123 GHz. The LNA provides a 3-dB bandwidth spanning from 118.6 - 155.9 GHz, corresponding to a fractional bandwidth (FBW) of 27.2%, which is the widest bandwidth among recently reported D-band CMOS LNAs. The design consumes 61.5 mW dc power, exhibits an input 1-dB gain compression point (IP_1dB) of -27 dBm, and occupies an area of 0.636