TY - GEN
T1 - A Clock-Free 200MS/s 10-bit Time-Interleaved SAR ADC
AU - Kuo, Chien Hung
AU - Luo, Zih Jyun
N1 - Publisher Copyright:
© 2019 Department of Microelectronics and Computer Science, Lodz University of Technology.
PY - 2019/6
Y1 - 2019/6
N2 - In this paper, a clock-free 200-MS/s 10-bit time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The presented SAR ADC can generate required clock by itself while an active signal is asserted. In the presented TI structure, two SAR ADCs are alternated with entering sample and comparison phases by the control circuit, and thus the equivalent sample rate can be doubled. The presented ADC is simulated under TSMC 90nm 1P9M CMOS process. Under a supply voltage of 1.2-V and an equivalent sampling rate of 200-MS/s, the resulted SNDR of the proposed ADC is 58.94 dB, which is equivalent to the ENOB of 9.50-bit. The simulated DNL and INL are within 0.735 /-0.404 and 0.734 /-0.552, respectively.
AB - In this paper, a clock-free 200-MS/s 10-bit time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The presented SAR ADC can generate required clock by itself while an active signal is asserted. In the presented TI structure, two SAR ADCs are alternated with entering sample and comparison phases by the control circuit, and thus the equivalent sample rate can be doubled. The presented ADC is simulated under TSMC 90nm 1P9M CMOS process. Under a supply voltage of 1.2-V and an equivalent sampling rate of 200-MS/s, the resulted SNDR of the proposed ADC is 58.94 dB, which is equivalent to the ENOB of 9.50-bit. The simulated DNL and INL are within 0.735 /-0.404 and 0.734 /-0.552, respectively.
KW - analog-To-digital converters
KW - clock-free
KW - successive approximation register
KW - time-interleaved
UR - http://www.scopus.com/inward/record.url?scp=85071336691&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85071336691&partnerID=8YFLogxK
U2 - 10.23919/MIXDES.2019.8787144
DO - 10.23919/MIXDES.2019.8787144
M3 - Conference contribution
AN - SCOPUS:85071336691
T3 - Proceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019
SP - 133
EP - 136
BT - Proceedings of the 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019
A2 - Napieralski, Andrzej
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2019
Y2 - 27 June 2019 through 29 June 2019
ER -