@inproceedings{c97e472561834ee8afb2e7744f18ef43,
title = "A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters",
abstract = "This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.",
keywords = "DPWM, Envelope modulation, LTE polar modulation transmitter",
author = "Kuo, {Chien Hung} and Jhang, {Cin De}",
year = "2013",
doi = "10.1109/VLSI-SoC.2013.6673314",
language = "English",
isbn = "9781479905249",
series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",
publisher = "IEEE Computer Society",
pages = "386--389",
booktitle = "2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings",
note = "2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 ; Conference date: 07-10-2013 Through 09-10-2013",
}