A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

Chien-Hung Kuo, Cin De Jhang

研究成果: 書貢獻/報告類型會議貢獻

摘要

This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.

原文英語
主出版物標題2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Proceedings
發行者IEEE Computer Society
頁面386-389
頁數4
ISBN(列印)9781479905249
DOIs
出版狀態已發佈 - 2013 一月 1
事件2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013 - Istanbul, 土耳其
持續時間: 2013 十月 72013 十月 9

出版系列

名字IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN(列印)2324-8432
ISSN(電子)2324-8440

其他

其他2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013
國家土耳其
城市Istanbul
期間13/10/713/10/9

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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