A bond graph representation of p-n junction diode using VHDL-AMS

This study focuses on the p-n junction diode modeling and simulation using bond graphs and VHDL-AMS. The bond graph modeling technique has been given an accommodated model for the interaction of power between elements on a system. The power flow is briefly sketched in the bond graph and the state equations are formulated directly from this graphical representation. Bond graph modeling is largely employed nowadays, and new techniques for structural analysis, model reduction as well as a certain number of software packages using bond graph have been developed. The bond graph methodology is a way to get a p-n junction diode model with important parameters to know the performance. VHDL is a modeling language which dedicates the discrete description to digital electronic hardware. Its extension VHDL-AMS allows modeling analogue subsystems and describing signal flow on a functional level. VHDL-AMS can be used as a unified modeling language for combined discrete-continuous system simulation. Once bond graphs are established, they can be easily described in VHDL-AMS. It will be possible to implement those models in any VHDL-AMS simulator. The system modeling yields equations, i.e. algebra and differential equations, and these equations have to be implemented into a reference simulator. The model is developed and simulated with the VHDL-AMS language under Dolphin SMASH environment.