A 7.5-12 GHz divide-by-256/260/264/268 frequency divider for frequency synthesizers

Jeng Han Tsai, Hung Da Shih

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

A 7.5-12 GHz divide-by-256/260/264/268 multi-modulus frequency divider with broadband and high-speed is demonstrated in this paper. The divider is implemented in standard 0.18-μm 1P6M CMOS technology. The frequency divider is composed of a divide-by-4 prescaler, a divide-by-4/5 dual-modulus divider, a divide-by-16 counter, and a digital control logic. Utilizing a CML without tail current source and a modified D-Flip-Flip (DFF) merged with NAND gate function. The operation frequency of the divider is from 7.5-12 GHz via an input signal power of 0 dBm. To further extend the operation frequency, we raise the input signal power of the divider. Providing an input signal power of 16 dBm, an extended operation frequency of the divider from 5 GHz to 13.3 GHz can be achieved. The lowest input sensitivity is about-15 dBm at 8 ∼ 9 GHz. The power consumption of whole divider is about 28.1 mW. The chip size is 0.45 × 0.66 mm 2 including all test pads.

原文英語
主出版物標題2012 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2012 - Proceedings
頁面1650-1653
頁數4
DOIs
出版狀態已發佈 - 2012 八月 10
事件2012 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2012 - Shenzhen, 中国
持續時間: 2012 五月 52012 五月 8

出版系列

名字2012 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2012 - Proceedings
5

其他

其他2012 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2012
國家/地區中国
城市Shenzhen
期間2012/05/052012/05/08

ASJC Scopus subject areas

  • 電氣與電子工程

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