A 7-12 GHz multi-modulus frequency divider

Jeng-Han Tsai, Yi Wei Chung, Hung Da Shih, Jian Ping Chou

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

A 7-12 GHz divide-by-256/260/264/268 multi-modulus frequency divider chain is designed and implemented in 0.18-μm CMOS technology. The frequency divider chain consists of a divide-by-4 divider, a divide-by-4/5 dual-modulus divider, a divide-by-16 counter, and digital control logic circuits. To speed up the operating frequency, a current mode logic (CML) divider without tail current source and a modified D-Flip-Flip (DFF) merged with NAND gate function are adopted. The multi-modulus frequency divider chain demonstrates high operating frequency of 7 GHz to 12 GHz while maintaining reasonable dc power consumption of 19.95 mW.

原文英語
主出版物標題2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
頁面1232-1234
頁數3
DOIs
出版狀態已發佈 - 2012 十二月 1
事件2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, 臺灣
持續時間: 2012 十二月 42012 十二月 7

出版系列

名字Asia-Pacific Microwave Conference Proceedings, APMC

其他

其他2012 Asia-Pacific Microwave Conference, APMC 2012
國家/地區臺灣
城市Kaohsiung
期間2012/12/042012/12/07

ASJC Scopus subject areas

  • 電氣與電子工程

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