A 7-12 GHz multi-modulus frequency divider

Jeng-Han Tsai, Yi Wei Chung, Hung Da Shih, Jian Ping Chou

研究成果: 書貢獻/報告類型會議貢獻

1 引文 斯高帕斯(Scopus)

摘要

A 7-12 GHz divide-by-256/260/264/268 multi-modulus frequency divider chain is designed and implemented in 0.18-μm CMOS technology. The frequency divider chain consists of a divide-by-4 divider, a divide-by-4/5 dual-modulus divider, a divide-by-16 counter, and digital control logic circuits. To speed up the operating frequency, a current mode logic (CML) divider without tail current source and a modified D-Flip-Flip (DFF) merged with NAND gate function are adopted. The multi-modulus frequency divider chain demonstrates high operating frequency of 7 GHz to 12 GHz while maintaining reasonable dc power consumption of 19.95 mW.

原文英語
主出版物標題2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
頁面1232-1234
頁數3
DOIs
出版狀態已發佈 - 2012 十二月 1
事件2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, 臺灣
持續時間: 2012 十二月 42012 十二月 7

出版系列

名字Asia-Pacific Microwave Conference Proceedings, APMC

其他

其他2012 Asia-Pacific Microwave Conference, APMC 2012
國家臺灣
城市Kaohsiung
期間12/12/412/12/7

    指紋

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

引用此

Tsai, J-H., Chung, Y. W., Shih, H. D., & Chou, J. P. (2012). A 7-12 GHz multi-modulus frequency divider. 於 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings (頁 1232-1234). [6421879] (Asia-Pacific Microwave Conference Proceedings, APMC). https://doi.org/10.1109/APMC.2012.6421879