A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai; Chung Han Wu; Hong Yuan Yang; Tian Wei Huang

doi:10.1109/LMWC.2011.2171929

A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai^*
, Chung Han Wu
, Hong Yuan Yang
, Tian Wei Huang

^*此作品的通信作者

電機工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

53 引文斯高帕斯（Scopus）

摘要

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P _sat of 10.72 dBm and OP _{1 dB} of 7.3 dBm from 1.2 V supply. After linearization, the OP _{1 dB} has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP _{1 dB} consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

原文	英語
文章編號	6070991
頁（從 - 到）	676-678
頁數	3
期刊	IEEE Microwave and Wireless Components Letters
卷	21
發行號	12
DOIs	https://doi.org/10.1109/LMWC.2011.2171929
出版狀態	已發佈 - 2011 12月

ASJC Scopus subject areas

凝聚態物理學
電氣與電子工程

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10.1109/LMWC.2011.2171929

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引用此

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title = "A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer",

abstract = "A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4\% to 10.8\%. The optimum improvement of the IMD3 is 25 dB.",

keywords = "60 GHz, CMOS, linearization, linearizer, power amplifier (PA), pre-distortion",

author = "Tsai, \{Jeng Han\} and Wu, \{Chung Han\} and Yang, \{Hong Yuan\} and Huang, \{Tian Wei\}",

note = "Funding Information: Manuscript received November 16, 2010; revised July 30, 2011; accepted October 02, 2011. Date of publication November 07, 2011; date of current version December 07, 2011. This work was supported in part by the National Science Council of Taiwan under Grant NSC 99-2219-E-002-011, Grant NSC 100-2219-E-002-007, Grant NSC 98-2221-E-003-024-MY2, and Grant NSC NSC 100-2221-E-003-027.",

year = "2011",

month = dec,

doi = "10.1109/LMWC.2011.2171929",

language = "English",

volume = "21",

pages = "676--678",

journal = "IEEE Microwave and Wireless Components Letters",

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AU - Tsai, Jeng Han

AU - Wu, Chung Han

AU - Yang, Hong Yuan

AU - Huang, Tian Wei

N1 - Funding Information: Manuscript received November 16, 2010; revised July 30, 2011; accepted October 02, 2011. Date of publication November 07, 2011; date of current version December 07, 2011. This work was supported in part by the National Science Council of Taiwan under Grant NSC 99-2219-E-002-011, Grant NSC 100-2219-E-002-007, Grant NSC 98-2221-E-003-024-MY2, and Grant NSC NSC 100-2221-E-003-027.

PY - 2011/12

Y1 - 2011/12

N2 - A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

AB - A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

KW - 60 GHz

KW - CMOS

KW - linearization

KW - linearizer

KW - power amplifier (PA)

KW - pre-distortion

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JO - IEEE Microwave and Wireless Components Letters

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A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

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