A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer

Jeng Han Tsai*, Chung Han Wu, Hong Yuan Yang, Tian Wei Huang

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

30 引文 斯高帕斯(Scopus)

摘要

A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a P sat of 10.72 dBm and OP 1 dB of 7.3 dBm from 1.2 V supply. After linearization, the OP 1 dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP 1 dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

原文英語
文章編號6070991
頁(從 - 到)676-678
頁數3
期刊IEEE Microwave and Wireless Components Letters
21
發行號12
DOIs
出版狀態已發佈 - 2011 十二月

ASJC Scopus subject areas

  • 凝聚態物理學
  • 電氣與電子工程

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