TY - GEN
T1 - A 5.5 GHz low-power PLL using 0.18-μm CMOS technology
AU - Tsai, Jeng Han
AU - Huang, Shao Wei
AU - Chou, Jian Ping
PY - 2014
Y1 - 2014
N2 - This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.
AB - This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.
KW - CMOS
KW - Phase-locked loop (PLL)
KW - lower power
KW - radio frequency integration circuit (RFIC)
UR - http://www.scopus.com/inward/record.url?scp=84904015823&partnerID=8YFLogxK
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U2 - 10.1109/RWS.2014.6830071
DO - 10.1109/RWS.2014.6830071
M3 - Conference contribution
AN - SCOPUS:84904015823
SN - 9781479921812
T3 - IEEE Radio and Wireless Symposium, RWS
SP - 205
EP - 207
BT - RWS 2014 - Proceedings
PB - IEEE Computer Society
T2 - 2014 IEEE Radio and Wireless Symposium, RWS 2014
Y2 - 19 January 2014 through 22 January 2014
ER -