A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Jeng Han Tsai, Shao Wei Huang, Jian Ping Chou

研究成果: 書貢獻/報告類型會議貢獻

3 引文 斯高帕斯(Scopus)

摘要

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

原文英語
主出版物標題RWS 2014 - Proceedings
主出版物子標題2014 IEEE Radio and Wireless Symposium
發行者IEEE Computer Society
頁面205-207
頁數3
ISBN(列印)9781479921812
DOIs
出版狀態已發佈 - 2014 一月 1
事件2014 IEEE Radio and Wireless Symposium, RWS 2014 - Newport Beach, CA, 美国
持續時間: 2014 一月 192014 一月 22

出版系列

名字IEEE Radio and Wireless Symposium, RWS
ISSN(列印)2164-2958
ISSN(電子)2164-2974

其他

其他2014 IEEE Radio and Wireless Symposium, RWS 2014
國家美国
城市Newport Beach, CA
期間14/1/1914/1/22

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Communication

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  • 引用此

    Tsai, J. H., Huang, S. W., & Chou, J. P. (2014). A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. 於 RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium (頁 205-207). [6830071] (IEEE Radio and Wireless Symposium, RWS). IEEE Computer Society. https://doi.org/10.1109/RWS.2014.6830071