TY - GEN
T1 - A 538Mbps 2×64 spatial permutation modulation detector for MIMO systems
AU - Chi, Jung Chun
AU - Yeh, Yu Cheng
AU - Lai, I. Wei
AU - Tsai, Pei Yun
AU - Huang, Yuan Hao
N1 - Publisher Copyright:
© 2020 IEEE
PY - 2020
Y1 - 2020
N2 - Spatial permutation modulation (SPM) is a new multiple-input-multiple-output (MIMO) technology for next-generation communication systems, which is an extension of spatial modulation (SM) that conveys data information at multiple time instants. By encoding the permutation of activated antennas at several time instants, the SPM system gains benefits of transmit and time diversities enabling reliable mobile communications. This study proposed a low-complexity SPM detector, called multiple-candidate-selection matching maximal ratio combining detector (MCSMMRC), for the SPM system. The MCSMMRC detector has very low complexity, fixed throughput, and scalable computing structure, which makes MCSMMD suitable for hardware implementation. This study designed and implemented the proposed MCSMMD detector by using a Xilinx Virtex-7 FPGA chip. The FPGA implementation results showed that it achieved a maximum throughput of 538 Mbps and exhibited better normalized throughput than those of other SM-based detector chips in the literature.
AB - Spatial permutation modulation (SPM) is a new multiple-input-multiple-output (MIMO) technology for next-generation communication systems, which is an extension of spatial modulation (SM) that conveys data information at multiple time instants. By encoding the permutation of activated antennas at several time instants, the SPM system gains benefits of transmit and time diversities enabling reliable mobile communications. This study proposed a low-complexity SPM detector, called multiple-candidate-selection matching maximal ratio combining detector (MCSMMRC), for the SPM system. The MCSMMRC detector has very low complexity, fixed throughput, and scalable computing structure, which makes MCSMMD suitable for hardware implementation. This study designed and implemented the proposed MCSMMD detector by using a Xilinx Virtex-7 FPGA chip. The FPGA implementation results showed that it achieved a maximum throughput of 538 Mbps and exhibited better normalized throughput than those of other SM-based detector chips in the literature.
KW - Generalized spatial modulation (GSM)
KW - Multiple-input-multiple-output (MIMO)
KW - Spatial modulation (SM)
KW - Spatial permutation modulation (SPM)
UR - http://www.scopus.com/inward/record.url?scp=85109297444&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85109297444&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:85109297444
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Y2 - 10 October 2020 through 21 October 2020
ER -