A 5.3-GHz 30.1-dBm Fully Integrated CMOS Power Amplifier With High-Power Built-In Linearizer

Jeng Han Tsai*

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

5 引文 斯高帕斯(Scopus)

摘要

— A 5.3-GHz watt-level fully integrated CMOS power amplifier (PA) with a high-power built-in linearizer is presented in this letter. Utilizing a transformer (TF)-based 2-stage dual-radial power splitting/combining structure, the CMOS PA achieves watt-level output power. To enhance the linearity of the CMOS PA, a cascode cold-FET built-in linearizer which has high power capacity is developed. The CMOS PA achieves 30.1-dBm saturation output power (Psat ), 27 dBm output 1-dB compression point (OP1dB ), 27.7 dB small signal gain, and 18% power added efficiency (PAE) at 5.3 GHz after linearization. Under the IEEE 802.11ac WLAN 20/80 MHz bandwidth 64/256 QAM OFDM modulated signals, the CMOS PA transmits linear output power (Plinear ) of 21/17 dBm with 5.6%/2.5% error vector magnitude (EVM), respectively. To our knowledge, the CMOS PA demonstrates the highest Plinear and OP1dB among other reported CMOS PAs around 5 GHz to date.

原文英語
頁(從 - 到)431-434
頁數4
期刊IEEE Microwave and Wireless Technology Letters
33
發行號4
DOIs
出版狀態已發佈 - 2023 4月 1

ASJC Scopus subject areas

  • 電氣與電子工程
  • 凝聚態物理學

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