A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were -90.88 and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets.
ASJC Scopus subject areas