A 5 GHz fully-integrated low-power phase-locked loop using 0.18-μm CMOS technology

Jeng Han Tsai, Chuan Jung Huang, Tse Yi Hsieh, Shao Wei Huang

研究成果: 雜誌貢獻期刊論文同行評審

摘要

A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were -90.88 and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets.

原文英語
頁(從 - 到)1534-1537
頁數4
期刊Microwave and Optical Technology Letters
58
發行號7
DOIs
出版狀態已發佈 - 2016 七月 1

ASJC Scopus subject areas

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 電氣與電子工程

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