A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition

Chua Chin Wang*, Ralph Gerard B. Sangalang, Chien Ping Kuo, Hsin Che Wu, Yi Hsu, Shen Fu Hsiao, Chia Hung Yeh

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

摘要

This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.

原文英語
頁(從 - 到)4860-4871
頁數12
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
69
發行號12
DOIs
出版狀態已發佈 - 2022 12月 1

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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