A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM

Chua Chin Wang*, Lean Karlo S. Tolentino, Chia Yi Huang, Chia Hung Yeh

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

摘要

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is $432.81 \times 510.265\,\,\mu \text{m}^{2}$. Among the related works, the proposed CIM performs the most number of operations and functions.

原文英語
頁(從 - 到)2172-2185
頁數14
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
29
發行號12
DOIs
出版狀態已發佈 - 2021 12月 1

ASJC Scopus subject areas

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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