A 30-60GHz cmos sub-harmonic IQ de/modulator for high data-rate communication system applications

Wei Heng Lin, Wei Lun Chang, Jeng Han Tsai, Tian Wei Huang

研究成果: 書貢獻/報告類型會議貢獻

9 引文 斯高帕斯(Scopus)

摘要

A 30-60 GHz sub-harmonic IQ de/modulator using TSMC CMOS 0.13-μm process is presented in this paper. The IQ de/modulator consists of two FET resistive mixers, a 90° coupler, and a Wilkinson power divider. The resistive mixer could simultaneously used as a up-converted or a down-converted mixer. Therefore, the measurement of the FET resistive mixer based modulator or demodulator will be done. The die size is 0.78 mm × 0.58 mm. Both IQ demodulator and modulator feature the conversion loss of - 16±1 dB and good demodulation and modulation capacity.

原文英語
主出版物標題RWS 2009 IEEE Radio and Wireless Symposium, Proceedings
頁面462-465
頁數4
DOIs
出版狀態已發佈 - 2009 七月 21
事件2009 IEEE Radio and Wireless Symposium, RWS 2009 - San Diego, CA, 美国
持續時間: 2008 一月 182008 一月 22

出版系列

名字RWS 2009 IEEE Radio and Wireless Symposium, Proceedings

其他

其他2009 IEEE Radio and Wireless Symposium, RWS 2009
國家美国
城市San Diego, CA
期間08/1/1808/1/22

    指紋

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此

Lin, W. H., Chang, W. L., Tsai, J. H., & Huang, T. W. (2009). A 30-60GHz cmos sub-harmonic IQ de/modulator for high data-rate communication system applications. 於 RWS 2009 IEEE Radio and Wireless Symposium, Proceedings (頁 462-465). [4957388] (RWS 2009 IEEE Radio and Wireless Symposium, Proceedings). https://doi.org/10.1109/RWS.2009.4957388