A 24-GHz 65-nm CMOS 3-D Radial and Vertically Stacked Transmitter Front-End IC for Vital-sign Detection Radar Applications

In contrast to the conventional horizontal routings in chip layout, a 24-GHz three dimensional transmitter front-end integrated circuit architecture with vertical signal paths implemented by a 1P9M 65-nm CMOS technology is proposed in this article. With the up-converison ring mixer located at the center of the layout with its traces routed on the bottom, and four power amplifier cells radially distributed on the four quadrants of the chip with their traces at the top metals, an ultra-small core area of 0.27 mm2 is occupied. Besides, layout symmetry is ensured and heat dissipation problem might be alleviated. The transmitter has a 3-dB bandwidth from 21 to 28 GHz. The measured conversion gain and saturation power (Psat) are 3 dB and 5.5 dBm, respectively, under 14 mW DC-power consumption (PDC) at 24 GHz.