A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.