A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process

Jeng Han Tsai*, Chia Lung Lin, Yin Ting Kuo

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

2 引文 斯高帕斯(Scopus)

摘要

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.

原文英語
頁(從 - 到)1750-1755
頁數6
期刊Microwave and Optical Technology Letters
59
發行號7
DOIs
出版狀態已發佈 - 2017 七月

ASJC Scopus subject areas

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 凝聚態物理學
  • 電氣與電子工程

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