A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process

Yung Nien Jen; Jeng Han Tsai; Chung Te Peng; Tian Wei Huang

doi:10.1109/LMWC.2008.2008591

A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process

Yung Nien Jen^*
, Jeng Han Tsai
, Chung Te Peng
, Tian Wei Huang

^*此作品的通信作者

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

47 引文斯高帕斯（Scopus）

摘要

A 2024 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 μm standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm², which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 W/mm ², which is the smallest one compared to all reported paper.

原文	英語
文章編號	4729652
頁（從 - 到）	42-44
頁數	3
期刊	IEEE Microwave and Wireless Components Letters
卷	19
發行號	1
DOIs	https://doi.org/10.1109/LMWC.2008.2008591
出版狀態	已發佈 - 2009 1月
對外發佈	是

ASJC Scopus subject areas

凝聚態物理學
電氣與電子工程

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10.1109/LMWC.2008.2008591

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title = "A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process",

abstract = "A 2024 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 μm standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7\% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 W/mm 2, which is the smallest one compared to all reported paper.",

keywords = "24 GHz, CMOS, Fully integrated, Power amplifier (PA)",

author = "Jen, \{Yung Nien\} and Tsai, \{Jeng Han\} and Peng, \{Chung Te\} and Huang, \{Tian Wei\}",

note = "Funding Information: Manuscript received August 14, 2008; revised September 16, 2008. First published December 22, 2008; current version published January 08, 2009. This work was supported by the National Science Council of Taiwan under Grant NSC 97-2219-E-002-021 and Grant NSC 97-2218-E-155-009 and by TSMC Semiconductors Corporation through the Chip Implementation Center (CIC), Taiwan..",

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N1 - Funding Information: Manuscript received August 14, 2008; revised September 16, 2008. First published December 22, 2008; current version published January 08, 2009. This work was supported by the National Science Council of Taiwan under Grant NSC 97-2219-E-002-021 and Grant NSC 97-2218-E-155-009 and by TSMC Semiconductors Corporation through the Chip Implementation Center (CIC), Taiwan..

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A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process

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