@article{b64c756f4b0f451e9a30fe5c25346b01,
title = "A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process",
abstract = "A 2024 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 μm standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 W/mm 2, which is the smallest one compared to all reported paper.",
keywords = "24 GHz, CMOS, Fully integrated, Power amplifier (PA)",
author = "Jen, {Yung Nien} and Tsai, {Jeng Han} and Peng, {Chung Te} and Huang, {Tian Wei}",
note = "Funding Information: Manuscript received August 14, 2008; revised September 16, 2008. First published December 22, 2008; current version published January 08, 2009. This work was supported by the National Science Council of Taiwan under Grant NSC 97-2219-E-002-021 and Grant NSC 97-2218-E-155-009 and by TSMC Semiconductors Corporation through the Chip Implementation Center (CIC), Taiwan..",
year = "2009",
month = jan,
doi = "10.1109/LMWC.2008.2008591",
language = "English",
volume = "19",
pages = "42--44",
journal = "IEEE Microwave and Wireless Components Letters",
issn = "1531-1309",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",
}