@inproceedings{a73ecdc1931b4bd3930785959dd39a39,
title = "A 128-phase delay-locked loop with cyclic VCDL",
abstract = "A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.",
keywords = "Clock generator, Cyclic VCDL, Multi-phase DLL",
author = "Kuo, {Chien Hung} and Ma, {Yu Chieh}",
year = "2013",
doi = "10.1109/ASQED.2013.6643555",
language = "English",
isbn = "9781479913145",
series = "Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013",
publisher = "IEEE Computer Society",
pages = "10--13",
booktitle = "Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013",
note = "5th Asia Symposium on Quality Electronic Design, ASQED 2013 ; Conference date: 26-08-2013 Through 28-08-2013",
}