A 128-phase delay-locked loop with cyclic VCDL

Chien Hung Kuo, Yu Chieh Ma

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.

原文英語
主出版物標題Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013
發行者IEEE Computer Society
頁面10-13
頁數4
ISBN(列印)9781479913145
DOIs
出版狀態已發佈 - 2013 一月 1
事件5th Asia Symposium on Quality Electronic Design, ASQED 2013 - Penang, 马来西亚
持續時間: 2013 八月 262013 八月 28

出版系列

名字Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013

其他

其他5th Asia Symposium on Quality Electronic Design, ASQED 2013
國家/地區马来西亚
城市Penang
期間2013/08/262013/08/28

ASJC Scopus subject areas

  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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