A 10-bit 2.5mW 0.27mm 22 CMOS DAC with spike-free switching

Chien Hung Kuo; Jen Chieh Tsai

A 10-bit 2.5mW 0.27mm ²2 CMOS DAC with spike-free switching

Chien Hung Kuo^*
, Jen Chieh Tsai

^*此作品的通信作者

研究成果: 會議貢獻類型 › 會議論文 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm ². The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.

原文	英語
頁面	473-476
頁數	4
出版狀態	已發佈 - 2005
對外發佈	是
事件	9th International Symposium on Consumer Electronics 2005, ISCE 2005 - , 澳门持續時間: 2005 6月 14 → 2005 6月 16

其他

其他	9th International Symposium on Consumer Electronics 2005, ISCE 2005
國家/地區	澳门
期間	2005/06/14 → 2005/06/16

ASJC Scopus subject areas

一般工程

其它文件與鏈接

引用此

@conference{ee28537e18bf4450a881889740f3f1b8,

title = "A 10-bit 2.5mW 0.27mm 22 CMOS DAC with spike-free switching",

abstract = "A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm 2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.",

keywords = "Current mirror, Digital-to-analog converter, Low power",

author = "Kuo, \{Chien Hung\} and Tsai, \{Jen Chieh\}",

year = "2005",

language = "English",

pages = "473--476",

note = "9th International Symposium on Consumer Electronics 2005, ISCE 2005 ; Conference date: 14-06-2005 Through 16-06-2005",

}

TY - CONF

T1 - A 10-bit 2.5mW 0.27mm 22 CMOS DAC with spike-free switching

AU - Kuo, Chien Hung

AU - Tsai, Jen Chieh

PY - 2005

Y1 - 2005

N2 - A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm 2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.

AB - A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm 2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.

KW - Current mirror

KW - Digital-to-analog converter

KW - Low power

UR - https://www.scopus.com/pages/publications/28444444973

UR - https://www.scopus.com/pages/publications/28444444973#tab=citedBy

M3 - Paper

AN - SCOPUS:28444444973

SP - 473

EP - 476

T2 - 9th International Symposium on Consumer Electronics 2005, ISCE 2005

Y2 - 14 June 2005 through 16 June 2005

ER -

A 10-bit 2.5mW 0.27mm 22 CMOS DAC with spike-free switching

摘要

其他

ASJC Scopus subject areas

其它文件與鏈接

指紋

引用此

A 10-bit 2.5mW 0.27mm ²2 CMOS DAC with spike-free switching