A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm 2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.
|出版狀態||已發佈 - 2005|
|事件||9th International Symposium on Consumer Electronics 2005, ISCE 2005 - , 澳门|
持續時間: 2005 六月 14 → 2005 六月 16
|其他||9th International Symposium on Consumer Electronics 2005, ISCE 2005|
|期間||2005/06/14 → 2005/06/16|
ASJC Scopus subject areas
- 工程 (全部)