A 10-bit 2.5mW 0.27mm 22 CMOS DAC with spike-free switching

Chien Hung Kuo*, Jen Chieh Tsai

*此作品的通信作者

研究成果: 會議貢獻類型會議論文同行評審

2 引文 斯高帕斯(Scopus)

摘要

A low-power digital-to-analog converter for portable electronics is introduced. A fully segmented architecture with a spike-free current mirror is presented to improve the INL/DNL and reduce the power consumption of the high-speed current steering DAC. The presented 10-bit DAC have been implemented in 0.18μm IP6M CMOS standard technology, and its core area is 0.27mm 2. The simulation results show the DNL/INL is ±0.14/0.14 at a conversion rate of 10MHz, and consume 2.5mW of power from a 1.8V supply voltage.

原文英語
頁面473-476
頁數4
出版狀態已發佈 - 2005
事件9th International Symposium on Consumer Electronics 2005, ISCE 2005 - , 澳门
持續時間: 2005 六月 142005 六月 16

其他

其他9th International Symposium on Consumer Electronics 2005, ISCE 2005
國家/地區澳门
期間2005/06/142005/06/16

ASJC Scopus subject areas

  • 工程 (全部)

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