A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched opamps

Chien Hung Kuo*, Shen Iuan Liu

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

12 引文 斯高帕斯(Scopus)

摘要

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-μm 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.

原文英語
頁(從 - 到)2041-2045
頁數5
期刊IEEE Journal of Solid-State Circuits
39
發行號11
DOIs
出版狀態已發佈 - 2004 十一月

ASJC Scopus subject areas

  • 電氣與電子工程

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