In this paper, a 0.8V switched-opamp (SOP)-based 22 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order ΔΣ modulator with CIFF-CIFB structure has been implemented in a 0.13μm CMOS 1P8M technology. The core area excluding PADs is 1.66×1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented ΔΣ modulator is 15.7 mW at a 0.8V of supply voltage.
|主出版物標題||Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems|
|出版狀態||已發佈 - 2008|
|事件||APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, 中国|
持續時間: 2008 十一月 30 → 2008 十二月 3
|其他||APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems|
|期間||2008/11/30 → 2008/12/03|
ASJC Scopus subject areas