A 0.7-mW V-Band Transformer-Based Positive- Feedback Receiver Front-End in a 65-nm CMOS

In this letter, we propose an ultralow-power transformer-based V-band receiver front-end using a 65-nm CMOS technology. Forward-body-bias and transformer-based positive-feedback topologies are utilized to enable its operation at a low drain bias of 0.3 V, while still ensuring its gain performance. A resistive ring mixer, with its advantage of zero-dc-power consumption, serves as the frequency down-converter of the system. The proposed receiver front-end demonstrates an 8.5-dB conversion gain and possesses the power-saving ability to use only 0.7 mW of dc-power consumption.