8-bit AES implementation in FPGA by multiplexing 32-bit AES operation

Chi Jeng Chang, Chi Wu Huang, Hung Yun Tai, Mao Yuan Lin

研究成果: 書貢獻/報告類型會議貢獻

4 引文 斯高帕斯(Scopus)

摘要

8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction-Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.

原文英語
主出版物標題Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
頁面505-507
頁數3
DOIs
出版狀態已發佈 - 2007 十二月 1
事件1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, 中国
持續時間: 2007 十一月 12007 十一月 3

出版系列

名字Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

其他

其他1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
國家中国
城市Chengdu
期間07/11/107/11/3

ASJC Scopus subject areas

  • Computer Science(all)
  • Economics, Econometrics and Finance (miscellaneous)

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