8-bit AES FPGA implementation using block RAM

Chi Jeng Chang, Chi Wu Huang, Hung Yun Tai, Mao Yuan Lin, Teng Kuei Hu

研究成果: 書貢獻/報告類型會議貢獻

13 引文 斯高帕斯(Scopus)

摘要

An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

原文英語
主出版物標題Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
頁面2654-2659
頁數6
DOIs
出版狀態已發佈 - 2007
事件33rd Annual Conference of the IEEE Industrial Electronics Society, IECON - Taipei, 臺灣
持續時間: 2007 十一月 52007 十一月 8

其他

其他33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
國家臺灣
城市Taipei
期間07/11/507/11/8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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