An 8-bit data-path AES implementation was proposed recently by Tim Good  as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.
|主出版物標題||Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON|
|出版狀態||已發佈 - 2007|
|事件||33rd Annual Conference of the IEEE Industrial Electronics Society, IECON - Taipei, 臺灣|
持續時間: 2007 十一月 5 → 2007 十一月 8
|其他||33rd Annual Conference of the IEEE Industrial Electronics Society, IECON|
|期間||2007/11/05 → 2007/11/08|
ASJC Scopus subject areas