5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

H. Alsuraisry, M. H. Wu, P. S. Huang, J. H. Tsai, T. W. Huang

研究成果: 雜誌貢獻文章

5 引文 斯高帕斯(Scopus)

摘要

A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.

原文英語
頁(從 - 到)1338-1340
頁數3
期刊Electronics Letters
52
發行號15
DOIs
出版狀態已發佈 - 2016 七月 21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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