TY - JOUR
T1 - 3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces
AU - Cheng, Hao En
AU - Wu, Ching Lin
AU - Lin, Chun Yu
N1 - Publisher Copyright:
© 2025 Elsevier Ltd
PY - 2025/11
Y1 - 2025/11
N2 - In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.
AB - In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.
KW - ESD protection circuit
KW - Mixed-voltage interface
KW - Negative voltage supply
UR - https://www.scopus.com/pages/publications/105008793795
UR - https://www.scopus.com/pages/publications/105008793795#tab=citedBy
U2 - 10.1016/j.sse.2025.109185
DO - 10.1016/j.sse.2025.109185
M3 - Article
AN - SCOPUS:105008793795
SN - 0038-1101
VL - 229
JO - Solid-State Electronics
JF - Solid-State Electronics
M1 - 109185
ER -