3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

Y. D. Lin; Y. T. Tang; S. S. Sheu; T. H. Hou; W. C. Lo; M. H. Lee; M. F. Chang; Y. C. King; C. J. Lin; H. Y. Lee; P. C. Yeh; H. Y. Yang; P. S. Yeh; C. Y. Wang; J. W. Su; S. H. Li

doi:10.1109/IEDM19573.2019.8993504

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrO_x

Y. D. Lin, Y. T. Tang, S. S. Sheu, T. H. Hou, W. C. Lo, M. H. Lee, M. F. Chang, Y. C. King, C. J. Lin, H. Y. Lee, P. C. Yeh, H. Y. Yang, P. S. Yeh, C. Y. Wang, J. W. Su, S. H. Li

光電工程學士學位學程

研究成果: 書貢獻/報告類型 › 會議論文篇章

21 引文斯高帕斯（Scopus）

摘要

The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrO_x FRAM technology that shows a wake-up free character, 10¹⁰/10⁹ endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial P_r = 25/18 μC/cm² for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at V_DD of 4V.

原文	英語
主出版物標題	2019 IEEE International Electron Devices Meeting, IEDM 2019
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993504
出版狀態	已發佈 - 2019 12月
事件	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, 美国持續時間: 2019 12月 7 → 2019 12月 11

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
卷	2019-December
ISSN（列印）	0163-1918

會議

會議	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
國家/地區	美国
城市	San Francisco
期間	2019/12/07 → 2019/12/11

ASJC Scopus subject areas

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

存取文件

10.1109/IEDM19573.2019.8993504

其它文件與鏈接

引用此

Lin, Y. D., Tang, Y. T., Sheu, S. S., Hou, T. H., Lo, W. C., Lee, M. H., Chang, M. F., King, Y. C., Lin, C. J., Lee, H. Y., Yeh, P. C., Yang, H. Y., Yeh, P. S., Wang, C. Y., Su, J. W., & Li, S. H. (2019). 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrO_x. 於 2019 IEEE International Electron Devices Meeting, IEDM 2019 文章 8993504 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993504

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrO_x. / Lin, Y. D.; Tang, Y. T.; Sheu, S. S. 等.
2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993504 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2019-December).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Lin, YD, Tang, YT, Sheu, SS, Hou, TH, Lo, WC, Lee, MH, Chang, MF, King, YC, Lin, CJ, Lee, HY, Yeh, PC, Yang, HY, Yeh, PS, Wang, CY, Su, JW & Li, SH 2019, 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrO_x. 於 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993504, Technical Digest - International Electron Devices Meeting, IEDM, 卷 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, 美国, 2019/12/07. https://doi.org/10.1109/IEDM19573.2019.8993504

Lin YD, Tang YT, Sheu SS, Hou TH, Lo WC, Lee MH 等. 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrO_x. 於 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8993504. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM19573.2019.8993504

@inproceedings{ca26f680cf6c43d7822d629e5fe010bf,

title = "3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx",

abstract = "The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrOx FRAM technology that shows a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at VDD of 4V.",

author = "Lin, {Y. D.} and Tang, {Y. T.} and Sheu, {S. S.} and Hou, {T. H.} and Lo, {W. C.} and Lee, {M. H.} and Chang, {M. F.} and King, {Y. C.} and Lin, {C. J.} and Lee, {H. Y.} and Yeh, {P. C.} and Yang, {H. Y.} and Yeh, {P. S.} and Wang, {C. Y.} and Su, {J. W.} and Li, {S. H.}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 ; Conference date: 07-12-2019 Through 11-12-2019",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993504",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

}

TY - GEN

T1 - 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

AU - Lin, Y. D.

AU - Tang, Y. T.

AU - Sheu, S. S.

AU - Hou, T. H.

AU - Lo, W. C.

AU - Lee, M. H.

AU - Chang, M. F.

AU - King, Y. C.

AU - Lin, C. J.

AU - Lee, H. Y.

AU - Yeh, P. C.

AU - Yang, H. Y.

AU - Yeh, P. S.

AU - Wang, C. Y.

AU - Su, J. W.

AU - Li, S. H.

PY - 2019/12

Y1 - 2019/12

N2 - The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrOx FRAM technology that shows a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at VDD of 4V.

AB - The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrOx FRAM technology that shows a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at VDD of 4V.

UR - http://www.scopus.com/inward/record.url?scp=85081066549&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85081066549&partnerID=8YFLogxK

U2 - 10.1109/IEDM19573.2019.8993504

DO - 10.1109/IEDM19573.2019.8993504

M3 - Conference contribution

AN - SCOPUS:85081066549

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019

Y2 - 7 December 2019 through 11 December 2019

ER -