2xVDD-Tolerant ESD Clamp with Dual Detection and Ultra-Low Leakage

Although conventional power-rail electrostatic discharge (ESD) clamp circuits are essential for ESD protection, they are prone to false triggering during fast power-on events. This phenomenon can lead to excessive current consumption and potential reliability concerns. Furthermore, leakage current exacerbates these issues by increasing static power dissipation and compromising long-term stability. To address these challenges, this study proposes a power-rail ESD clamp circuit that is tolerant to 2xVDD. This circuit incorporates a dual detection mechanism, integrating time detection and voltage detection to prevent false triggering during fast power-on events. Additionally, N-well and deep N-well isolation techniques are employed to effectively suppress parasitic NPN structures, thereby reducing leakage current and enhancing ESD robustness. The proposed circuit is implemented using the TSMC 180 nm CMOS process. Measurement results indicate that at room temperature, the leakage current is maintained at the level of nanoampere, and the circuit achieves a human-body-model (HBM) ESD robustness exceeding 8 kV. Even under 2xVDD operation, the design maintains ultra-low leakage current and exhibits excellent ESD protection capabilities, thereby improving energy efficiency and long-term reliability.