2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun-Yu Lin, Ming Dou Ker

研究成果: 書貢獻/報告類型會議貢獻

2 引文 (Scopus)

摘要

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

原文英語
主出版物標題ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題Nano-Bio Circuit Fabrics and Systems
頁面3417-3420
頁數4
DOIs
出版狀態已發佈 - 2010 八月 31
事件2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, 法国
持續時間: 2010 五月 302010 六月 2

出版系列

名字ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

其他

其他2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家法国
城市Paris
期間10/5/3010/6/2

指紋

Clamping devices
Rails
Networks (circuits)
Electric potential
Thyristors
Leakage currents

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

Lin, C-Y., & Ker, M. D. (2010). 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (頁 3417-3420). [5537864] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537864

2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. / Lin, Chun-Yu; Ker, Ming Dou.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420 5537864 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

研究成果: 書貢獻/報告類型會議貢獻

Lin, C-Y & Ker, MD 2010, 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537864, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 頁 3417-3420, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 法国, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537864
Lin C-Y, Ker MD. 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. 於 ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420. 5537864. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537864
Lin, Chun-Yu ; Ker, Ming Dou. / 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. 頁 3417-3420 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).
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