2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun-Yu Lin*, Ming Dou Ker

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

原文英語
主出版物標題ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
主出版物子標題Nano-Bio Circuit Fabrics and Systems
頁面3417-3420
頁數4
DOIs
出版狀態已發佈 - 2010 八月 31
事件2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, 法国
持續時間: 2010 五月 302010 六月 2

出版系列

名字ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

其他

其他2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
國家/地區法国
城市Paris
期間2010/05/302010/06/02

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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