使用90nm CMOS製程設計一轉換增益24.6±1.5 dB、雜訊指數5.6±0.8 dB及34.4mW之58~66GHz接收機前端電路

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

引用此

@article{3242d1f569a24f7b889cf1f8db7262ae,

title = "使用90nm CMOS製程設計一轉換增益24.6±1.5 dB、雜訊指數5.6±0.8 dB及34.4mW之58\textasciitilde{}66GHz接收機前端電路",

author = "李仁豪",

year = "2015",

language = "繁體中文",

volume = "22",

journal = "國家奈米元件實驗室奈米通訊",

issn = "1029-502x",

publisher = "國家實驗研究院國家奈米元件實驗室",

number = "3",

}