以完美雜湊優化樣式比對記憶體架構設計

Memory architectures have been widely adopted in network intrusion detection system for inspecting malicious packets due to their flexibility and scalability. Memory architectures match input streams against thousands of attack patterns by traversing the corresponding state transition table stored in commodity memories. With the increasing number of attack patterns, reducing memory requirement has become critical for memory architectures. In this project, we propose a novel memory architecture using perfect hashing to condense state transition tables without hash collisions. The proposed memory architecture achieves up to 99.5% improvement in memory reduction compared to the traditional two-dimensional memory architecture. We have implemented our memory architectures on graphic processing units and tested using attack patterns from Snort V2.8 and input packets from DEFCON. The experimental results show that the proposed memory architectures outperform state-of-the-art memory architectures both on performance and memory efficiency. The research results have been presented at 31st Annual IEEE International Conference on Computer Communications (INFOCOM), Eighth ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), GPU Technology Conference (GTC), and IEEE Transactions on Computers.