Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1990 Dec 1|
|Event||1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA|
Duration: 1990 May 1 → 1990 May 3
ASJC Scopus subject areas
- Electrical and Electronic Engineering