Via minimization with associated constraints in three-layer routing problem

Sung Chuan Fang, Kuo En Chang, Wu Shiung Feng

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.

Original languageEnglish
Pages (from-to)1632-1635
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
Publication statusPublished - 1990 Dec 1
Event1990 IEEE International Symposium on Circuits and Systems Part 3 (of 4) - New Orleans, LA, USA
Duration: 1990 May 11990 May 3

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Heuristic algorithms
Polychlorinated biphenyls
Wire

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Via minimization with associated constraints in three-layer routing problem. / Fang, Sung Chuan; Chang, Kuo En; Feng, Wu Shiung.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.12.1990, p. 1632-1635.

Research output: Contribution to journalConference article

@article{29c3744c23dd4fa3b2deb4278aea1bdd,
title = "Via minimization with associated constraints in three-layer routing problem",
abstract = "Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.",
author = "Fang, {Sung Chuan} and Chang, {Kuo En} and Feng, {Wu Shiung}",
year = "1990",
month = "12",
day = "1",
language = "English",
volume = "2",
pages = "1632--1635",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Via minimization with associated constraints in three-layer routing problem

AU - Fang, Sung Chuan

AU - Chang, Kuo En

AU - Feng, Wu Shiung

PY - 1990/12/1

Y1 - 1990/12/1

N2 - Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.

AB - Via minimization is the same as the layer assignment problem in VLSI or PCB routing. It consists of determining which layers can be used for routing the wire segments such that the number of vias can be minimized. A heuristic algorithm is presented to globally eliminate the vias in the three-layer channel routing. Some associated constraints, such as restricted terminals and adjacent limitation, are addressed extensively. According to the results, the algorithm is fast and efficient, thus generating very good results.

UR - http://www.scopus.com/inward/record.url?scp=0025692528&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025692528&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0025692528

VL - 2

SP - 1632

EP - 1635

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -