Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin; Pin Hsin Chang; Rong Kun Chang; Ming Dou Ker; Wen Tai Wang

doi:10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming Dou Ker, Wen Tai Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

Original language	English
Title of host publication	Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	255-258
Number of pages	4
ISBN (Electronic)	9781479999286, 9781479999286
DOIs	https://doi.org/10.1109/IPFA.2015.7224380
Publication status	Published - 2015 Aug 25
Event	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan Duration: 2015 Jun 29 → 2015 Jul 2

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2015-August

Other

Other	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Country/Territory	Taiwan
City	Hsinchu
Period	2015/06/29 → 2015/07/02

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/IPFA.2015.7224380

Cite this

Lin, C. Y., Chang, P. H., Chang, R. K., Ker, M. D., & Wang, W. T. (2015). Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 (pp. 255-258). Article 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. / Lin, Chun Yu; Chang, Pin Hsin; Chang, Rong Kun et al.
Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 255-258 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY, Chang, PH, Chang, RK, Ker, MD & Wang, WT 2015, Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. in Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015., 7224380, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. 255-258, 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015, Hsinchu, Taiwan, 2015/06/29. https://doi.org/10.1109/IPFA.2015.7224380

Lin CY, Chang PH, Chang RK, Ker MD, Wang WT. Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 255-258. 7224380. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2015.7224380

Lin, Chun Yu ; Chang, Pin Hsin ; Chang, Rong Kun et al. / Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 255-258 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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abstract = "A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.",

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Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

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