TY - GEN
T1 - Using wavelet transform and partial distance search to implement kNN classifier on FPGA with multiple modules
AU - Li, Hui Ya
AU - Yeh, Yao Jung
AU - Hwang, Wen-Jyi
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper presents a novel algorithm of using wavelet transform and partial distance search (PDS) to realize the kNN classifier on field programmable gate array (FPGA) with multiple modules. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the PDS in the wavelet domain, and allows concurrent classification of different input vectors for further computation acceleration by employing multiple-module PDS. For the effective reduction of the area complexity and computation latency, we proposed a novel PDS algorithm well-suited for hardware implementation and also employ subspace search, bitplane reduction and multiplecoefficient accumulation techniques. The proposed realization has been embedded in a softcore CPU for physical performance measurements. Experimental results show that the proposed realization not only provides a cost-effective solution to the FPGA implementation of kNN classification systems, but also meets both high throughput and low area cost.
AB - This paper presents a novel algorithm of using wavelet transform and partial distance search (PDS) to realize the kNN classifier on field programmable gate array (FPGA) with multiple modules. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the PDS in the wavelet domain, and allows concurrent classification of different input vectors for further computation acceleration by employing multiple-module PDS. For the effective reduction of the area complexity and computation latency, we proposed a novel PDS algorithm well-suited for hardware implementation and also employ subspace search, bitplane reduction and multiplecoefficient accumulation techniques. The proposed realization has been embedded in a softcore CPU for physical performance measurements. Experimental results show that the proposed realization not only provides a cost-effective solution to the FPGA implementation of kNN classification systems, but also meets both high throughput and low area cost.
KW - FPGA implementation
KW - Nonparametric classification
KW - Partial distance search
KW - Pattern recognition
KW - kNN classifier
UR - http://www.scopus.com/inward/record.url?scp=37849015548&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=37849015548&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:37849015548
SN - 9783540742586
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 1105
EP - 1116
BT - Image Analysis and Recognition - 4th International Conference, ICIAR 2007, Proceedings
T2 - 4th International Conference on Image Analysis and Recognition, ICIAR 2007
Y2 - 22 August 2007 through 24 August 2007
ER -