Abstract
We report a low-temperature InP p-MOS with a high capacitance density of 2.7 μF/ cm2 , low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high- κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.
Original language | English |
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Pages (from-to) | 2810-2813 |
Number of pages | 4 |
Journal | Journal of Nanoscience and Nanotechnology |
Volume | 15 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2015 Jan 1 |
Keywords
- Equivalent oxide thickness (EOT)
- Indium phosphide (InP)
- TiLaO
ASJC Scopus subject areas
- Bioengineering
- Chemistry(all)
- Biomedical Engineering
- Materials Science(all)
- Condensed Matter Physics