TiO2 -based indium phosphide metal-oxide-semiconductor capacitor with high capacitance density

Chun Hu Cheng, Hsiao Hsuan Hsu, Kun I. Chou

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We report a low-temperature InP p-MOS with a high capacitance density of 2.7 μF/ cm2 , low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high- κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.

Original languageEnglish
Pages (from-to)2810-2813
Number of pages4
JournalJournal of Nanoscience and Nanotechnology
Volume15
Issue number4
DOIs
Publication statusPublished - 2015 Jan 1

Fingerprint

Indium phosphide
Semiconductors
indium phosphides
metal oxide semiconductors
Oxides
capacitors
Buffers
Capacitors
leakage
Capacitance
capacitance
Metals
Equipment and Supplies
Temperature
Buffer layers
current distribution
Leakage currents
CMOS
buffers
indium phosphide

Keywords

  • Equivalent oxide thickness (EOT)
  • Indium phosphide (InP)
  • TiLaO

ASJC Scopus subject areas

  • Bioengineering
  • Chemistry(all)
  • Biomedical Engineering
  • Materials Science(all)
  • Condensed Matter Physics

Cite this

TiO2 -based indium phosphide metal-oxide-semiconductor capacitor with high capacitance density. / Cheng, Chun Hu; Hsu, Hsiao Hsuan; Chou, Kun I.

In: Journal of Nanoscience and Nanotechnology, Vol. 15, No. 4, 01.01.2015, p. 2810-2813.

Research output: Contribution to journalArticle

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AB - We report a low-temperature InP p-MOS with a high capacitance density of 2.7 μF/ cm2 , low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high- κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.

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