Thin Relaxed SiGe Layers for Strained Si CMOS

P. S. Chen, S. W. Lee, Min-Hung Lee, C. W. Liu, M. J. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High quality, low cost and smooth surface of thin relaxed SiGe layers on new buffers are fabricated This SiGe nanostructure buffers help thin SiGe uniform layers to relax by introducing some dislocations networks. With these novel Si/Ge buffer, the reduction of thickness of relaxed SiGe uniform layer are from 50 to 75% . The mobility enhancement of the strained Si n-MOSFET deposited on theses relaxed SiGe layer/SiGe buffers are 8 to 40% higher than that of controlled compositional graded SiGe buffers. Such thin relaxed SiGe layerson these new buffers proves to be useful approach to fabricate high quality relaxed epilayers with large lattice mismatch.

Original languageEnglish
Title of host publication2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW
Pages79-82
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW - , Taiwan
Duration: 2004 Sep 92004 Sep 10

Publication series

Name2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW

Other

Other2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW
CountryTaiwan
Period04/9/904/9/10

Fingerprint

Lattice mismatch
Epilayers
Nanostructures
Costs

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, P. S., Lee, S. W., Lee, M-H., Liu, C. W., & Tsai, M. J. (2004). Thin Relaxed SiGe Layers for Strained Si CMOS. In 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW (pp. 79-82). (2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW).

Thin Relaxed SiGe Layers for Strained Si CMOS. / Chen, P. S.; Lee, S. W.; Lee, Min-Hung; Liu, C. W.; Tsai, M. J.

2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW. 2004. p. 79-82 (2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chen, PS, Lee, SW, Lee, M-H, Liu, CW & Tsai, MJ 2004, Thin Relaxed SiGe Layers for Strained Si CMOS. in 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW. 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW, pp. 79-82, 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW, Taiwan, 04/9/9.
Chen PS, Lee SW, Lee M-H, Liu CW, Tsai MJ. Thin Relaxed SiGe Layers for Strained Si CMOS. In 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW. 2004. p. 79-82. (2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW).
Chen, P. S. ; Lee, S. W. ; Lee, Min-Hung ; Liu, C. W. ; Tsai, M. J. / Thin Relaxed SiGe Layers for Strained Si CMOS. 2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW. 2004. pp. 79-82 (2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW).
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